1. Field of the Invention
The present invention relates to the field of scan testing; more particularly, the present invention relates to a method and apparatus for performing scan testing that reduces the number of control signals, avoids bus contention, and reduces the number of constraints in test generation.
2. Description of Related Art
A typical integrated circuit has combinational logic blocks which are coupled through latches controlled by a system clock. In order to test the functionality and performance of a combinational logic block, various combinations of stimulus conditions are selected according to well-known methods. In order to apply the desired stimulus to a combinational logic block, a sequence of operations may need to be performed. In a complex integrated circuit, the time to apply this sequence of operations to apply this stimulus can be burdensome.
Internal scan testing is a well-known technique to serially accept data that is applied to critical inputs of these combinational logic blocks. The ability to directly control internal signals simplifies the preparation process for a test of the combinational logic. Multiple scan cells are serially coupled to produce the scan chain. Each of the scan cells also have an input that is coupled to an output of one combinational logic block and an output that is coupled to the input of another combinational logic block.
The following method is used to perform stuck-at fault testing. First, a sequence of bits are applied to the head of the scan chain until all the scan cells have been initialized to the proper value. Second, each scan cell applies the data to the input of the corresponding combination block in response to a first pulse on the system clock. Third, another scan cell samples an output of that combinational block in response to a second pulse on the system clock. Fourth, the responses of the combinational blocks are serially shifted out of the tail of the scan chain to be compared against expected values. Should there be a fault on a critical signal of that combinational block, the response will not correspond to the expected value and the device will fail the test. Faults include open circuits, short circuits, and aberrations in resistance and/or capacitance, for example.
Alternatively, some scan cells are capable of generating a transition on the input of the combinational logic block to enable testing of the performance (delay) of the combinational logic block to determine the maximum frequency of operation. The following method is used to perform delay fault testing. First, the initial values and their complements are loaded into latches within each scan cell. Second, the initial value is applied to the input of the corresponding combination block in response to a first clock pulse on the system clock. Third, the final value is applied to the input of the corresponding combination block (thereby generating a transition) in response to a second clock pulse on the system clock. Fourth, another scan cell samples an output of that combinational block in response to a third clock pulse on the system clock. Fifth, the responses of the combinational blocks are serially shifted out of the tail of the scan chain to be compared against expected values. The time between the second clock pulse and the third clock pulse can be gradually decreased and the test repeated until the response sampled is incorrect. The minimum passing time would correspond to the minimum period of operation of that combinational logic block for that particular stimulus. By applying a sequence of various worst case stimulus conditions, the maximum frequency of operation may be determined.
One apparatus for performing internal scan is illustrated in FIG. 1. It is described more fully in "Design For Testability: Using Scanpath Techniques For Path Delay Test and Measurement," Institute of Electrical & Electronic Engineers (IEEE) International Test Conference 1991, pp. 365-374, by B. Dervisoglu and G. Strong.
A master latch 100 is coupled to receive a data (D) signal which is an output from a first combinational logic block. This D signal is latched in response to an active-low enable signal (EN1#). A logic OR gate 130 is coupled to receive a system clock and a double-strobe (DS) control signal and generate the EN1# signal. The master latch 100 is also coupled to receive a scan-in (SI) signal which is strobed in response to a master load (ML) control signal. The output (Q1#) signal is the complement of the latched signal.
A slave latch 110 is coupled to latch the Q1# signal in response to the system clock. In addition, the slave latch 110 is coupled to latch the scan-in (SI) signal in response to a scan-in clock (SI.sub.-- CLK). The slave latch 110 generates the latched signal (Q2) and its complement (Q). The Q signal is coupled to an input of a second combinational block. Since the D and SI signals are complemented by the master latch 100 and then complemented by the slave latch 110, the resulting signal is the input signal and not its complement.
A scan slave latch 120 is coupled to latch the Q2 signal in response to a scan-out clock (SO.sub.-- CLK). The scan slave latch 120 drives the latched data on a scan-out (SO) signal. The SI signal that is latched by the slave latch 110 and then by the scan slave latch 120 is not complemented. However, the D signal is complemented by the master latch 100. When the complement of the D signal is serially scanned out through the slave latch 110 and the scan slave latch 120 for comparison with the expected response, it remains the complement of the D signal. External logic that is used to analyze the scan results must test for the complement of the expected combinational logic block outputs.
During normal functional operation, the DS and ML control signals are deasserted. The output of the first combinational logic block is latched by the master latch 100 to generate the Q1# signal in response to the system clock being deasserted. The Q1# signal is latched by the slave latch 110 to generate the Q signal in response to the system clock being asserted. The Q signal is applied to the input of the second combinational logic block. Therefore, in the normal functional mode of operation, an output of the first combinational logic block is driven to an input of the next combinational logic block on each rising edge of the clock signal.
During stuck at fault testing, the DS and ML control signals are deasserted. Each scan cell is initialized by scanning in data through the slave latch 110 and then through the scan slave latch 120 by applying an alternating sequence of pulses of the SI.sub.-- CLK and the SO.sub.-- CLK signals. Note that as the values serially shift through the slave latch 110, the Q signal (which is the input to the second combinational logic block) toggles according to the value being shifted through the scan cell. By applying the CLK signal, the master latch of another scan cell samples the response of the second combinational logic block to the test data is applied. The sampled values for each scan cell is then shifted through the scan chain for comparison with expected values by applying an alternating sequence of pulses of the SI.sub.-- CLK and the SO.sub.-- CLK signals.
During delay fault testing, the slave latch 110 is initialized with the initial value and the master latch is initialized with the complement of the final value of the input to define a transition (from initial value to final value) which is to be applied to the second combination logic block. The DS and ML control signals are asserted to cause the master latch 100 and the slave latch 110 to latch the same SI signal in response to the SI.sub.-- CLK signal. However, since the SI signal is inverted once by the slave latch 110 to produce the initial value and the SI signal is inverted twice by the master latch 100 and the slave latch 110 to produce the final value, the initial value is the complement of the SI signal and the final value is the SI signal. As in the case of stuck at fault testing, as the values serially shift through the slave latch 110, the Q signal (which is the input to the second combinational logic block) toggles according to the value being shifted through the scan cell. When the scan is complete the transition is applied to the input of the second combinational logic block in response to a first pulse of the system clock. The DS signal must be deasserted after the first pulse because otherwise the D signal may corrupt the final value latched by the master latch 100. The master latch of another scan cell samples the output of the second combinational logic block in response to a second pulse of the system clock. The DS signal must be deasserted before the second pulse of the system clock in order to enable the master latch 100 to latch the response of the second combinational logic block. The sampled values for each scan cell is then shifted through the scan chain for comparison with expected values. The time between the first and second pulses of the system clock is gradually reduced and the test repeated until the device does not produce the expected values.
One problem with the scan cell described above is that two control signals (the DS and ML signals) are required to operate the scan cell. A reduction of signals required to perform internal scan testing is particularly desirable because it reduces the number of signals that need to be routed to each scan cell. The reduction of control signals also reduces complexity of scan control logic.
Furthermore, the DS control signal is timing sensitive in that it must be deasserted after the first pulse of the system clock but before the second pulse of the system clock. Timing sensitive control signals add complexity and cost to the design of the integrated circuit and the external system that drives the timing sensitive control signal by requiring that the control signal be carefully routed.
Another problem with the scan cell described above is that the input to the combinational logic blocks transition as data is scanned through the scan chain. A scan cell that toggles the input of the combinational logic block during scan shift operations is known as a destructive scan cell. In some cases, the random combinations that are applied to the inputs of the combinational logic blocks during the serial scan operations may cause bus contention problems. For example, if two scan cells drive different select inputs to a multiplexer and both cells happen to enable their corresponding select inputs at the same time as the data is being scanned through the scan chain, the multiplexer would be allowing two inputs to simultaneously drive the same bus. If these inputs happen to be driving the bus to different logic values, a direct-current (DC) path from power to ground is created which increases power consumption and may lead to reliability problems. It is desirable to use a scan cell that does not toggle the input of the combinational logic block during scan shift (a non-destructive scan cell).
A disadvantage of using destructive scan cells to perform transitional fault testing is that some combinations of transitions may not be available due to test constraints. In one method of transitional fault testing, the transition stimulus is applied to the combinational logic blocks in response to the last assertion of the scan clock signal during the shift sequence. For example, assume that there is a scan cell A coupled to a scan cell B to form a scan cell chain and the data sequence of D1, D2, and D3 is applied to the scan chain. On the last assertion of the scan clock, scan cell A transitions from D2 to D3 and scan cell B transitions from D1 to D2. Note that D2 is used to define the transition of scan cell A and the transition of scan cell B. Therefore, this method cannot be used to cause the value scan cell A transitions from and the value scan cell B transitions to, to be different. Such a combination of transitions may be desired.
In another method of transitional fault testing, a first value is scanned into a first scan latch and a second value is scanned into a second scan latch. In response to a first system clock, the first value is applied to a first combinational logic block and the second value is applied to a second combinational logic block (the block to be tested). The second scan latch receives an output of the first combinational logic block (third value) and applies that output to the second combinational logic block in response to a second system clock. Thus, the input to the second combinational block transitions from the second value to the third value in response to the second system clock and an output of the second combinational logic block is latched by a third scan latch in response to a third system clock. One disadvantage of this method is that automatic test program generation (ATPG) tools that determine the combination of transitions that are desired to test to the second combinational logic block must evaluate both the first combinational logic block and the second combinational logic block to determine the first and second values which will generate the desired transition. This requires a more complex ATPG tool and more simulation time to generate test sequences.
What is needed is a method and apparatus to perform stuck-at and delay fault testing using internal scan cells without requiring control signals, particularly timing sensitive control signals, and without toggling the output driving a combinational logic block during serial scan operations.